A typical television broadcast station transmits video signals in standard resolution. When the video signals are received by a video signal receiver, the standard resolution is expanded if the resolution of the display associated with the video signal receiver is higher than the standard resolution, compressed if the resolution of the display is less than the standard resolution, or left unchanged if the resolution of the display is the same as the standard resolution. A conventional video signal receiver includes a main-channel format converter (“MFC”) for expanding or compressing the resolution of the received video signal. The MFC includes a horizontal format converter (“HFC”) for performing resolution conversion in the horizontal direction and a vertical format converter (“VFC”) for performing resolution conversion in the vertical direction.
Typical VFC designs require line memories to store video lines for vertical resolution expansion or compression. In a through mode input and output formats are the same; so the VFC merely requires 1 new input line for every output line that it produces. But to perform a resolution compression, the VFC often needs to take in more than one input line to produce an output line. For example, in a ⅔ resolution compression the VFC uses 12 input lines to produce 8 output lines. Resolution compression may require the VFC to use varying numbers of input lines to produce a series of output lines. In the ⅔ resolution compression, for example, the conventional VFC toggles between 1 and 2 new input lines for every output line that it produces.
The optimum bandwidth for a given vertical resolution compression is approximately equal to the inverse of the resolution compression ratio times the bandwidth of the input lines. To continue the example, the optimum bandwidth for the ⅔ resolution compression is about 1.5 times the bandwidth of the input signal. However, in typical implementations the VFC will need significantly more than the optimum bandwidth. For the ⅔ resolution compression, typical implementations require 2 (or more) times the bandwidth of the input in order to meet the highest bandwidth peak for all output lines, which occurs if two input lines are written to the line memories during the time of one output line. The high bandwidth requirements strain available resources within integrated circuits (“ICs”) that implement VFCs, driving up system clock speeds and/or memory bus sizes.
A significant contributor to the high bandwidth requirements of the typical VFC implementation is that generation of each output line is not started until after all of the respective input lines are fully stored in memory. Another drawback of typical VFC implementations is that new input lines (i.e., input lines needed to generate future output lines) are not written to the line memories until after the data for the present output line is fully read from the memories. Another drawback of typical VFC implementations is that processing is suspended during the vertical blanking interval. Such drawbacks fail to fully utilize the line memories for reduction of the overall VFC processing bandwidth.
The present invention is directed to overcoming the drawbacks discussed above.